1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of performing fin cut etch processes for taper FinFET semiconductor devices and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1 is a plan view of an illustrative prior art integrated circuit product 100 including a plurality of fins 105 formed in a semiconductor substrate 110. In this example, the product 100 includes a first FinFET device 115 having three illustrative fins 105 and a gate structure 120 formed above the fins 105. A second FinFET device 125 has two illustrative fins 105 and a gate structure 130 formed above the fins 105. An active region 135 is defined by the fins 105. Due to the difference in the number of fins 105 for each device 115, 125, the active region 135 is not rectangular. This arrangement is referred to as a tapered device in that the active region 135 is not rectangular. The active region 135 includes a taper 140 in the area that would otherwise be occupied by a portion of the lowermost fin 105 if it had the same length as the two uppermost fins 105. The use of tapered devices allows higher density layouts as compared to forming a separate active region for each device 115, 125, each having a rectangular shape.
To form the product 100, a portion of the fin 105 corresponding to the taper 140 in the active region 135 is removed. Typically, the fins 105 are formed in a regular array. To define separate transistor devices, the length of the fins may be adjusted and some fins or portions of fins may be removed, such as to form the tapered active region 135. For example, a fin cut or “FC cut” process cuts fins in the direction that crosses the plurality of fins 105 by removing fin portions inside of and exposed by the FC cut mask. An active region cut process, or “RX cut” process removes one or more of the fin segments in a direction parallel to the plurality of fins 105 by removing fin portions located outside of and exposed by the RX cut mask. In an RX cut process for a taper FinFET device, only a portion of the length of the fins) is removed. The dielectric material above the fin portions to be removed is removed to expose the tops of the underlying fin portions. A subsequent isotropic etch process removes the exposed fin portions. An isotropic etch process is used to avoid alignment problems associated with anisotropic etch processes given the small pitch of the fins. Alignment errors may result in leaving unwanted portions of fins or damaging remaining fins if an anisotropic etch were to be used. Because only the top surface is exposed during the isotropic etch, the etch front moves generally vertically downward from the exposed top of the fin toward the substrate. However, due to the nature of the isotropic etch process, the end portions of the fin portions that are intended to be retained are significantly undercut in a direction along the axial length of the fin. The degree of undercutting must be considered when designing the device.
FIGS. 2A-2B are cross-section views of a device 200 showing a fin 205 defined above a substrate 210. The fin may be defined using a variety of materials, such as silicon, an alloy of silicon, such as silicon germanium, or other semiconducting materials. In FIGS. 2A-2B, the cross-section is taken through the long axis of the fin 205. An oxide cap layer 215 and a nitride cap layer 220 (previously used as hard mask layers to pattern the fin 205 in the substrate 210) are present above a portion 205A of the fin 205 to be retained after the RX cut process. A portion 205B of the fin 205 is to be removed during the RX cut process. Liners 225, 230 may be formed on ends and the sidewalls of the fin 205. The liners 225, 230 on the end of the portion 205B that is opposite the portion 205A were previously removed during the FC cut process. The cap layers 215, 220 were selectively removed from the portion 205B so that the fin segment 205B can be removed during the RX cut process. The cap layers 215, 220 remain positioned above the portion 205A.
FIG. 2B illustrates the device 200 after the RX cut process was performed. The portion 205B is isotropically etched from the top down using the generally vertical etch front described above due to the presence of the liners 225, 230 on the sidewalls of the fin 205 (not visible in FIG. 2A or FIG. 2B). Due to the length of time needed to etch the portion 205B so as to insure its complete removal, the isotropic RX cut etch process erodes the end surface 205E, thereby reducing the length of the portion 205A that is intended to be part of an operational device. It is difficult to accurately estimate this length reduction and provide process repeatability.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.